In the field of semiconductor packaging, a through silicon via (TSV) is mainly used for allowing wires on the top surface and the bottom surface to be electrically connected to each other. Distinguished from the conventional semiconductor packaging, through the disposition of the TSV, a plurality of chips within a semiconductor packaging may provide an enhancement of the packaging density of the semiconductor packaging structure, a reduction of the size of the semiconductor packaging structure, an increment of the speed of the device, a reduction of signal delay and power consumption. Accordingly, the development of the TSV technology is advantageous for electronic product miniaturization due to the semiconductor packaging industrial attention to the TSV.
In present, the manufacturing process of the TSV is normally performed after the manufacture of a semiconductor device layer in the semiconductor manufacturing process. In general, a through hole is required to be formed on a wafer during the manufacture of the TSV. For example, the required through hole for forming the TSV may be achieved by an etching process on the back side of the wafer until the formed through hole exposes a complementary metal-oxide semiconductor. Alternatively, the through hole may be formed by an etching process on the front side of the wafer until the through hole extends to the back side of the wafer. The technique of etching the wafer from the front side may possibly damage a metal-oxide semiconductor while the technique of etching the wafer from the back side may prevent an adverse impact on the complementary metal-oxide semiconductor. Therefore, the technique of etching the wafer from the back side to form the through hole grows and becomes mainstream. Nonetheless, due to a higher aspect ratio of the through hole penetrating the wafer, when to stop the etching procedure is difficult to be determined. Hence, the researchers may encounter difficulties in controlling the etching depth of the through hole so that the wafer may not be completely etched or may be over-etched at which the through hole is located. When the through hole is not etched completely, the wires in the complementary metal-oxide semiconductor layer may not be exposed by the through hole and may not be connected to a conductor in the through hole. Thus, an open circuit occurs between the wires and the conductor in the through hole. When the over-etching occurs, notches may be formed at the interface between the substrate and the complementary metal-oxide semiconductor device layer in the wafer, the notches may lead to difficulties in the deposition of an insulting liner layer. For example, the deposition thickness of the insulting liner layer on the notches may be insufficient or the insulting liner layer may be non-continuous on the notches, and therefore the notches may result in electrical leakages. The reliability and the manufacturing yield of the semiconductor structure may be adversely affected.
In view of the foregoing, to properly control the process recipe of a conductive through via to prevent the aforementioned notches during the manufacturing process becomes an important issue.